New Delhi, Aug 17 (IANS) The Department of Space’s Semi-Conductor Laboratory (SCL), Mohali, and the Indian Institute of Technology, Bombay (IITB) have collaborated to successfully demonstrate CMOS 180nm-based production-ready 8-bit memory technology, described as a “gamechanger by enabling secure memory and encryption hardware for the country” by top scientists.
“The focus on electronics hardware including integrated circuits or chips is key to strengthen R&D primarily in the space and defence sectors. Development of standards, product design or IP development, and semiconductor manufacturing are increasingly important. The partnership between IIT Bombay and SCL to establish this memory technology for the first time demonstrates the augmented potential for semiconductor research in the country,” Govt’s Principal Scientific Adviser, Prof K. VijayRaghavan, said.
For successfully demonstrating CMOS 180nm based production-ready 8-bit memory technology, IIT Bombay invented the one-time programmable (OTP) memory based on ultra-thin deposited silicon dioxide (a few atoms thick) instead of the existing gate oxide-based OTP technology. “
In contrast to the high voltage required by gate oxide breakdown (a popular OTP memory), IIT Bombay’s memory chip requires less power and chip-area as the need for boosted voltage supply is avoided,” a release from the Scientific Advisor’s office said.
Stating that “memory technology is critical to data security, and it is essential for present and future Indian Fabs,” NITI Aayog Member, Dr V.K. Saraswat, said: “To infuse innovation, translating memory technology from research to manufacturing is the key to compete globally and serve locally to establish a vibrant semiconductor ecosystem. The OTP Memory Technology Adoption for Trimming Application by the joint IIT Bombay-SCL Chandigarh teams is a pioneering step in this direction. It will be a gamechanger by enabling secure memory and encryption hardware for the country.”
For the uninitiated, the analogue (as in natural world) output is converted into the language of computers (digital) through a digitiser chip or an analogue to digital converter.
Foundries mass-produce these chips. Ideally, these chips should be identical, but manufacturing variations produce tiny offsets which are revealed upon testing. This renders a large fraction of chips useless.
“The tiny offset may be stored in memory once and applied to the output afterward to make each imperfect chip ‘perfect’! Using this method, generic chips can now be designed, and application-specific offsets added to make expensive custom chip design redundant, saving time and money for the user,” the release said, explaining the importance of the new collaboration.
Chip technology gaps became the focus of investigation for Indian researchers as the demand for semiconductors increased in the country and globally. The government took cognizance of the significance of R&D in innovation-driven semiconductor manufacturing, and improved R&D capacity by building Centres for Excellence in Nanoelectronics (CENs); the first ones being at IIT Bombay and the Indian Institute of Science (IISc). This led to a transformed semiconductor research ecosystem making the country a major contributor to electron device-related research.
The next challenge was to translate research to manufacturing. The semiconductor manufacturing ecosystem in India is led by SCL, Mohali and is the most advanced semiconductor manufacturing fab (a large facility with cleanroom environments used to produce memory chips) in the country.
The team at IIT Bombay was supported by the Department of Science and Technology’s Intensification of Research in High Priority Area (IRHPA). Aspects of the work, funded by MeitY/DST’s Nanoelectronics Network for Research and Applications (NNetRA), supports the memory application, DST-Advanced Manufacturing Technologies, and the Office of PSA for hardware security. The team at IIT Bombay partnered with IIT Delhi, SETS Chennai, and DRDO for hardware encryption.
“One out of 100 ideas make the journey from Lab to Fab. The exacting process of exceeding 95 per cent yield requires an unrelenting multi-disciplinary team supported by a world-class R&D infrastructure to form an enduring collaboration. Once successful such technology opens possibilities of touching countless lives, in this case, through chips with a tiny memory,” said Professor Udayan Ganguly, who lead the team at IIT Bombay.